Serial communications buses are commonly used to facilitate the transport of data and clock signals from one device to another device over one or more serial communications lines that make up the bus. The Inter-Integrated Circuit (I2C) is a two-wire serial bus that is used to interconnect low speed electronic peripherals such as motherboards, processors, cellphones, analog to digital converters, digital to analog converters or other electronic devices.
A block diagram depicting an exemplary I2C system is illustrated in FIG. 1. As illustrated, the I2C serial communications bus employs two bidirectional serial lines; namely, a Serial Data Line (SDA) and a Serial Clock Line (SCL). The SDA and SCL lines are each coupled to a voltage Vdd via respective pull-up resistors R1 and R2. The serial clock and data lines are pulled down by open drain or open collector transistors located on one of the connected devices in accordance with the applicable signaling protocol. The I2C protocol is well known in the art and for that reason is not discussed further herein. I2C systems may include one or more masters and one or more slave devices coupled to the SDA and SDL lines. Typically the voltage Vdd is between 1.2 and 3.3 volts. Other voltages for Vdd may be employed.
When the SDA and SCL lines are not used for communication, these lines are pulled up to Vdd by the respective pull-up resistors. The electronic devices connected to the SDA and SCL lines of the serial communications bus, however, may employ supply voltages that are greater than or equal to the voltage Vdd. In order for the master or slave devices to properly interpret the signals on the SDA and SCL lines, they need to know the magnitude of the Vdd voltage. Typically, this is accomplished by providing a direct electrical connection from the voltage Vdd to a pin on an integrated circuit package containing the integrated circuit for the serial communications bus interface. The input circuitry within the interface circuit on the master or slave device, as applicable, uses the voltage Vdd to interpret the logic levels on the SDA and SCL lines.
It is costly to provide a dedicated connection from the voltage Vdd to an integrated circuit that provides the I2C interface for several reasons. First, a dedicated connection on an integrated circuit for the Vdd voltage connection requires additional area on the semiconductor device. Second, a dedicated connection for Vdd, requires another pin in the semiconductor package which may in turn require a larger package than might otherwise be required.
For the above reasons, it would be desirable to provide an integrated circuit in the form of an interface to a serial communications bus that avoids the above-described disadvantages.